MT41K256M16TW-107 IT:P DRAM Chip DDR3L SDRAM 4Gbit 256Mx16 1.35V IC

• Customization: Available
• Conductive Type: Unipolar Integrated Circuit
• Integration: LSI
• Model NO.: MT41K256M16TW-107 IT:P
• Technics: Thick Film IC
• MFG.: MICRON
• D/C: 22+
• Package: FBGA96
• Quality: Genuine New Original
• shape: Round
• Transport Package: Box
• Origin: China
• HS Code: 8542390000
• Production Capacity: 1000000PCS

Product Description

Description

MT41K256M16TW-107 IT:P : SDRAM - DDR3L Memory IC 4Gbit Parallel 933 MHz 20 ns 96-FBGA (8x14)

Mfr. Part#: MT41K256M16TW-107 IT:P

Mfr.: MICRON

Datasheet: (e-mail or chat us for PDF file)

ROHS Status: 

Quality: 100% Original

Warranty: ONE YEAR
 

 

Memory Type	Volatile
Memory Format	DRAM
Technology	SDRAM - DDR3L
Memory Size	4Gbit
Memory Organization	256M x 16
Memory Interface	Parallel
Clock Frequency	933 MHz
Write Cycle Time - Word, Page	-
Access Time	20 ns
Voltage - Supply	1.283V ~ 1.45V
Operating Temperature	-40°C ~ 95°C (TC)
Mounting Type	Surface Mount
Package / Case	96-TFBGA
Supplier Device Package	96-FBGA (8x14)
Base Product Number	MT41K256M16

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle atthe I/O pins. Asingle read orwrite operation forthe DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM inputreceiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CKandCK#). The crossing ofCKgoingHIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode.

 

Why choosing us

• Located in Shenzhen, the electronic market center of China.
• 100% guarantee components quality: Genuine Original.
• Sufficient stock on your urgent demand.
• Sophisticated colleagues help you solve problems to reduce your risk with on-demand manufacturing
• Faster shipment: In stock components can ship the same day .
• 24 Hours service 

 

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