| Customization: | Available |
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| Conductive Type: | Bipolar Integrated Circuit |
| Integration: | GSI |
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XC2C512-7FTG256C : COMPLEX-EEPLD, 512-CELL, 7.5NS PROP DELAY, 256 Pin, Plastic, BGA
Mfr. Part#: XC2C512-7FTG256C
Datasheet: 
(e-mail or chat us for PDF file)
ROHS Status:
Quality: 100% Original
Warranty: ONE YEAR
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Series
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CoolRunner II
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Packaging
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Tray
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Part Status
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Obsolete
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Programmable Type
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In System Programmable
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Delay Time tpd(1) Max
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7.1 ns
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Voltage Supply - Internal
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1.7V ~ 1.9V
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Number of Logic Elements/Blocks
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32
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Number of Macrocells
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512
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Number of Gates
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12000
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Number of I/O
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212
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Operating Temperature
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0°C ~ 70°C (TA)
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Mounting Type
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Surface Mount
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Package / Case
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256-LBGA
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Supplier Device Package
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256-FTBGA (17x17)
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Base Product Number
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XC2C512
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The CoolRunner-II 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of thirty two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies. The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature.
Applications
• Automotive Camera Modules
• Image Sensor Power
• Microprocessor Rails
• Automotive Infotainment Head Units
• Automotive Body Electronics
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