GD5F1GM7UEYIGR GD5F1GM7 nand flash 1Gbit 2.7V~3.6V 133MHz SPI Memory IC

• Customization: Available
• Conductive Type: Bipolar Integrated Circuit
• Integration: GSI
• Model NO.: GD5F1GM7UEYIGR
• Operating Temperature: -55℃ - 125℃
• Shape: Flat
• Technics: Semiconductor IC
• MFR.: GIGADEVICE
• D/C: 24+
• Package: WSON8
• Product status: Active
• Quality: Genuine New Original
• Transport Package: Box
• Specification: integrated circuit
• Origin: China
• HS Code: 8542399000
• Production Capacity: 1000000PCS
• Package Size: 20.00cm * 20.00cm * 5.00cm
• Package Gross Weight: 1.000kg

Product Description

description

GD5F1GM7UEYIGR:   1Gbit 2.7V~3.6V 133MHz SPI WSON8(6x8) Memory (ICs) RoHS

Mfr. Part#:  GD5F1GM7UEYIGR

Datasheet: (e-mail or chat us for PDF file)

ROHS Status: 

Quality: 100% Original

Warranty: ONE YEAR

 

 

Package	WSON8(6x8)
Memory Size	1Gbit
Voltage - Supply	2.7V~3.6V
Operating temperature	-40ºC~+85ºC
Program / Erase Cycles	80,000 cycles
Clock Frequency	133MHz
Data Retention - TDR (Year)	10 Years
Block Erase Time(tBE)	3ms
Write Cycle Time(tWC)	-
Page Programming Time (Tpp)	320us
Interface	SPI
Standby Supply Current	50uA

  

 

SPI (Serial Peripheral Interface) NAND Flash provides an ultra-cost effective while high density non-volatile memory storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive alternative to SPI-NOR and standard parallel NAND Flash, with advanced features. • Total pin count is 8, including VCC and GND • Density is 1Gb • Superior write performance and cost per bit over SPI-NOR • Significant low cost than parallel NAND This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the same pin out from one density to another. The command sets resemble common SPI-NOR command sets, modified to handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash memory, with specified designed features to ease host management: • User-selectable internal ECC. ECC parity is generated internally during a page program operation. When a page is read to the cache register, the ECC parity is detected and corrects the errors when necessary. The 64-bytes spare area is available even when internal ECC enabled. The device outputs corrected data and returns an ECC error status. • Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage collection task, without need of shift in and out of data. • Power on Read with internal ECC. The device will automatically read first page of fist block to cache after power on, then host can directly read data from cache for easy boot. Also the data is promised correct by internal ECC when ECC enabled. It is programmed and read in page-based operations, and erased in block-based operations. Data is transferred to or from the NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest to I/O control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as a data buffer for the NAND Flash memory array operation. The cache register functions as the buffer memory to enable page and random data READ/WRITE and copy back operations. These devices also use a SPI status register that reports the status of device operation.
 

 

 

 

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• Located in Shenzhen, the electronic market center of China.
• 100% guarantee components quality: Genuine Original.
• Sufficient stock on your urgent demand.
• Sophisticated colleagues help you solve problems to reduce your risk with on-demand manufacturing
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