| Customization: | Available |
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| Conductive Type: | Bipolar Integrated Circuit |
| Integration: | GSI |
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K4UBE3D4AB-MGCL : FBGA-200 DDR SDRAM ROHS
Mfr. Part#: K4UBE3D4AB-MGCL
Datasheet: 
(e-mail or chat us for PDF file)
ROHS Status:
Quality: 100% Original
Warranty: ONE YEAR
| Category | Memory/DDR SDRAM |
| Package | FBGA-200 |
Key Features
• Double-data rate architecture; two data transfers per clock cycle
• Bidirectional data strobes (DQS_t, DQS_c), These are transmitted/received with data to be used in capturing data at the receiver
• Differential clock inputs (CK_t and CK_c)
• Differential data strobes (DQS_t and DQS_c)
• Commands & addresses entered positive CK edges; data and data mask referenced to both edges of DQS
• 2channel composition per die
• 8 internal banks for each channel
• DMI Pin : DBI (Data Bus Inversion) when normal write and read operation, Data mask (DM) for masked write when DBI off - Counting # of DQ's 1 for masked write when DBI on
• Burst Length: 16, 32 (OTF)
• Burst Type: Sequential
• Read & Write latency : Refer to Table 13.4 AC Timing
• Auto Precharge option for each burst access
• Configurable Drive Strength
• Refresh and Self Refresh Modes
• Partial Array Self Refresh and Temperature Compensated Self Refresh
• Write Leveling
• CA Calibration
• Internal VREF and VREF training
• FIFO based write/read training
• MPC (Multi Purpose Command)
• LVSTLE (Low Voltage Swing Terminated Logic Extension) IO
• VDD1/VDD2/VDDQ : 1.8V/1.1V/0.6V
• VSSQ Termination
• No DLL : CK to DQS is not synchronized
• Edge aligned data output, write training for data input center align
• Refresh rate : 3.9us
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