DDR2 SDRAM W971GG6SB25I IC DRAM 1GBIT PARALLEL 84WBGA W971GG6SB25I-TR

• Customization: Available
• Conductive Type: Unipolar Integrated Circuit
• Integration: MSI
• Model NO.: W971GG6SB25I
• Technics: Thin Film IC
• MFG.: WINBOND
• D/C: 17+
• Package: WBGA-84
• Quality: Genuine New Original
• shape: SMD
• Transport Package: Box
• Origin: China
• HS Code: 8542390000
• Production Capacity: 1000000PCS

Product Description

Description

W971GG6SB25I: 8M X 8 Banks X 16 BIT DDR2 SDRAM

Package: WBGA-84

Mfr. Part#: W971GG6SB25I

Mfr.:WINBOND

Datasheet: (e-mail or chat us for PDF file)

ROHS Status: 

Quality: 100% Original

Warranty: 180 days

 

Product Status	Obsolete
Memory Type	Volatile
Memory Format	DRAM
Technology	SDRAM - DDR2
Memory Size	1Gbit
Memory Organization	64M x 16
Memory Interface	Parallel
Clock Frequency	200 MHz
Write Cycle Time - Word, Page	15ns
Access Time	400 ps
Voltage - Supply	1.7V ~ 1.9V
Operating Temperature	-40°C ~ 95°C (TC)
Mounting Type	Surface Mount
Package / Case	84-TFBGA
Supplier Device Package	84-WBGA (8x12.5)
Base Product Number	W971GG6

 

1. GENERAL DESCRIPTION

The W971GG6SB is a 1G bits DDR2 SDRAM, organized as 8,388,608 words 8 banks 16 bits. This

device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for various applications.

W971GG6SB is sorted into the following grade parts: -18, 18I, -25, 25I and -3. The -18 and 18I grade

parts are compliant to the DDR2-1066 (6-6-6) specification (the 18I industrial grade which is

guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -25 and 25I grade parts are compliant to the

DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade which is guaranteed to

support -40°C ≤ TCASE ≤ 95°C). The -3 grade parts is compliant to the DDR2-667 (5-5-5) specification.

All of the control and address inputs are synchronized with a pair of externally supplied differential

clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All

I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source

synchronous fashion.

2. FEATURES

Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V

Double Data Rate architecture: two data transfers per clock cycle

CAS Latency: 3, 4, 5, 6 and 7

Burst Length: 4 and 8

Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data

Edge-aligned with Read data and center-aligned with Write data

DLL aligns DQ and DQS transitions with clock

Differential clock inputs (CLK and CLK )

Data masks (DM) for write data

Commands entered on each positive CLK edge, data and data mask are referenced to both edges

of DQS

Posted CAS programmable additive latency supported to make command and data bus efficiency

Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)

Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal

quality

Auto-precharge operation for read and write bursts

Auto Refresh and Self Refresh modes

Precharged Power Down and Active Power Down

Write Data Mask

Write Latency = Read Latency - 1 (WL = RL - 1)

Interface: SSTL_18

Packaged in WBGA 84 Ball (8x12.5 mm2 ), using Lead free materials with RoHS compliant

 

Why choosing us

• Located in Shenzhen, the electronic market center of China.
• 100% guarantee components quality: Genuine Original.
• Sufficient stock on your urgent demand.
• Sophisticated colleagues help you solve problems to reduce your risk with on-demand manufacturing
• Faster shipment: In stock components can ship the same day .
• 24 Hours service 

 

Notice:

1. Product images are for reference only.
2. You can contact sales person to apply for a better price.
3.  For more products, Pls do not hesitate to contact our Sales team.