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W9751G6NB-25 : DRAM Chip DDR2 SDRAM 512Mbit 32Mx16 1.8V 84-Pin VFBGA
Mfr. Part#: W9751G6NB-25
Datasheet: 
(e-mail or chat us for PDF file)
ROHS Status:
Quality: 100% Original
Warranty: ONE YEAR
| Product Category: | DRAM |
| Type: | SDRAM - DDR2 |
| Memory Size: | 512 Mbit |
| Data Bus Width: | 16 bit |
| Maximum Clock Frequency: | 400 MHz |
| Package / Case: | VFBGA-84 |
| Organization: | 32 M x 16 |
| Access Time: | 400 ps |
| Supply Voltage - Min: | 1.7 V |
| Supply Voltage - Max: | 1.9 V |
| Minimum Operating Temperature: | 0 C |
| Maximum Operating Temperature: | + 85 C |
| Series: | W9751G6NB |
| Packaging: | Tray |
| Moisture Sensitive: | Yes |
| Mounting Style: | SMD/SMT |
| Product Type: | DRAM |
| Factory Pack Quantity: | 209 |
| Subcategory: | Memory & Data Storage |
| Supply Current - Max: | 90 mA |
The W9751G6NB is a 512M bits DDR2 SDRAM, organized as 8,388,608 words x 4 banks x 16 bits. This device achieves high speed transfer rates up to 1066 Mbps (DDR2-1066) for various applications. W9751G6NB is sorted into the following speed grades: -18, -25, -3, 18I, 25I, -3I, 18J, 25J and -3J. The -18, 18I and 18J grade parts are compliant to the DDR2-1066 (7-7-7) specification (the 18I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 18J industrial plus grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C). The -25, 25I and 25J grade parts are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 25J industrial plus grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C). The -3, -3I and -3J grade parts are compliant to the DDR2-667 (5-5-5) specification (the -3I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the -3J industrial plus grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK I/Os are synchronized with a single ended DQS or differential DQS DQS falling). All pair in a source synchronous fashion.
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