ENC28J60/SS Ethernet CTLR Single Chip 10Mbps 3.3V IC

• Customization: Available
• Conductive Type: Unipolar Integrated Circuit
• Integration: ULSI
• Model NO.: ENC28J60/SS
• Technics: Thin Film IC
• MFG.: MICROCHIP
• D/C: 17+
• Package: SSOP-28
• Quality: Genuine New Original
• shape: SMD
• Transport Package: Box
• Origin: China
• HS Code: 8542390000
• Production Capacity: 1000000PCS

Product Description

Description

ENC28J60/SS: Ethernet CTLR Single Chip 10Mbps 3.3V 28-Pin SSOP Tube

Package: SSOP-28

Mfr. Part#: ENC28J60/SS

Mfr.: MICROCHIP
Datasheet: (e-mail or chat us for PDF file)

ROHS Status: 

Quality: 100% Original

Warranty: 180 days
 

Product Status	Active
Protocol	Ethernet
Function	Controller
Interface	SPI
Standards	10 Base-T PHY
Voltage - Supply	3.1V ~ 3.6V
Current - Supply	160mA
Operating Temperature	0°C ~ 70°C
Package / Case	28-SSOP (0.209", 5.30mm Width)
Supplier Device Package	28-SSOP
Base Product Number	ENC28J60

 

The ENC28J60 is a stand-alone Ethernet controller with an industry standard Serial Peripheral Interface (SPI). It is designed to serve as an Ethernet network interface for any controller equipped with SPI. The ENC28J60 meets all of the IEEE 802.3 specifications. It incorporates a number of packet filtering schemes to limit incoming packets. It also provides an internal DMA module for fast data throughput and hardware assisted checksum calculation, which is used in various network protocols. Communication with the host controller is implemented via an interrupt pin and the SPI, with clock rates of up to 20 MHz. Two dedicated pins are used for LED link and network activity indication

Key Features

• Ethernet Controller Features
• IEEE 802.3ô Compatible Ethernet Controller
• Fully Compatible with 10/100/1000Base-T Networks
• Integrated MAC and 10Base-T PHY
• Supports One 10Base-T Port with Automatic Polarity Detection and Correction
• Supports Full and Half-Duplex modes
• Programmable Automatic Retransmit on Collision
• Programmable Padding and CRC Generation
• Programmable Automatic Rejection of Erroneous Packets
• SPI Interface with Clock Speeds Up to 20 MHz Buffer
• 8-Kbyte Transmit/Receive Packet Dual Port SRAM
• Configurable Transmit/Receive Buffer Size
• Hardware Managed Circular Receive FIFO
• Byte-Wide Random and Sequential Access with Auto-Increment
• Internal DMA for Fast Data Movement
• Hardware Assisted Checksum Calculation for Various Network Protocols Medium Access Controller (MAC) Features
• Supports Unicast, Multicast and Broadcast Packets
• Programmable Receive Packet Filtering and Wake-up Host on Logical AND or OR of the Following: - Unicast destination address - Multicast address - Broadcast address - Magic Packetô - Group destination addresses as defined by 64-bit Hash Table - Programmable Pattern Matching of up to 64 bytes at user-defined offset Physical Layer (PHY) Features
• Loopback mode
• Two Programmable LED Outputs for LINK, TX, RX, Collision and Full/Half-Duplex Status

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• Located in Shenzhen, the electronic market center of China.
• 100% guarantee components quality: Genuine Original.
• Sufficient stock on your urgent demand.
• Sophisticated colleagues help you solve problems to reduce your risk with on-demand manufacturing
• Faster shipment: In stock components can ship the same day .
• 24 Hours service 

 

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