IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip

Product Details
Customization: Available
Conductive Type: Bipolar Integrated Circuit
Integration: MSI
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  • IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip
  • IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip
  • IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip
  • IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip
  • IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip
  • IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip
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Basic Info.

Model NO.
IP1810
MFG.
ICPLUS
D/C
20+
Package
LQFP128
Quality
Genuine New Original
shape
LQFP128
Transport Package
Box
Origin
China
HS Code
8542390000
Production Capacity
1000000PCS

Product Description

Description

IP1810:  IP1810 is a non-blocking, store-and-forward architecture switch controller, which builds 8-port

10/100Mbps Fast Ethernet MAC and PHY, 1-port GMAC with RGMII interface and 1-port with RGMII/MII
for external CPU in a single chip.

Package: LQFP128

Mfr. Part#: IP1810

Mfr.: ICPLUS

Datasheet: IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip(e-mail or chat us for PDF file)

ROHS Status: IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip

Quality: 100% Original

Warranty: ONE YEAR

IP1810 is a non-blocking, store-and-forward architecture switch controller, which builds 8-port
10/100Mbps Fast Ethernet MAC and PHY, 1-port GMAC with RGMII interface and 1-port with RGMII/MII
for external CPU in a single chip.
IP1810 embeds a 4Mb SRAM for the use of packet buffer. It also provides various 2-wire interfaces,
such as CPU interface, SMI, and EEPROM interface, which allow the user to access the internal register,
external PHY's registers and EEPROM data. The serial LED can show the status of each port (such as
Link, Speed, Activity and so on) by using 74HC164 or IP403 external device through 2-wire (LEDCLK,
LEDDAT) signals driving from IP1810.
For avoiding loop occur, IP1810 supports STP, RSTP and MSTP. Even a hardware loop detection
mechanism is supported.
There are 16K entries in Lookup table. Hashing method can be selected either direct or CRC hashing
for MAC address learning. Lookup Table aging time can be adjustable ranging from 55 seconds to 500
hours. IP1810 also provides the MAC learning threshold to limit the number of addresses learning.
An independent Multicast table supports 256 entries. For the Internet Group Management Protocol,
IP1810 supports IGMP v1/v2/v3 for IPv4 and MLD v1/v2 for IPv6 packet snooping and aging time
function. For the IGMPv3 and MLDv2 application, IP1810 provides up to 10 sets IPv4 or 4 sets IPv6
address per entry for source list table.
IP1810 has 4k entries for 802.1Q VLAN, which provides more security for VLAN member, and
supports Independent VLAN Learning (IVL) and Share VLAN Learning (SVL). Further, IP1810 also has
add/remove C-tag, S-tag, VLAN remarking, uplink link port and inactive VID redirect functions for the
flexible VLAN application.
IP1810 has 128 entries for ACL table. The ACL (Address Control List) function provides advanced and
flexible control mechanism to decide what packet should do (action) if packet matches ACL rule. ACL
Rule and action:
z
Rules: (Port ID, DA, SA, DA/SA, DIP, SIP, TCP/UDP Port Number (DP and SP) )
z
Actions: (Sniffer, Insert/remove Tag, Priority, Redirection, Trap to CPU, BW limited, DSCP,
sFlow, Drop, PTP, MIB Counter)
For the Quality of Service application, IP1810 supports port-based, 802.1Q tag based, ACL based, IP
CoS/DSCP based, SMAC based, IP address based, IGMP based and WAN/LAN based to decide the
priority of output frame. For the Remarking application, IP1810 supports remarking for the DSCP, Ctag
and Stag value of transmit packet.
For the link aggregation application, IP1810 provides eight hashing methods (Port ID, DA, SA, DA/SA,
DIP, SIP, DP, and SP) and support six trunk groups' sets.
For meeting the various network applications, IP1810 also supports storm control, bandwidth rate
control, Output Queues functions, Sniffer, sFlow, PTP, MIB counters and eight LED display modes.
Therefore, IP1810 has the best adaptability and capability for the future network conditions.
IP1810 supports the web based management interface, such as Microsoft Internet Explorer or Mozilla
Firefox, Google chrome, user can more easily configure IP1810's functions by these browsers, and no
extra program is needed. Besides, IP1810 also provides IRMP(IC+ remote management protocol) to let
the users remotely configure the registers of IP1810.

 

Features List
8-Port 10/100Mb + 2-Port 10/100/1000Mb
Ethernet Switch
- Built-in 8 10/100Mb PHYs
- RGMII interface for 1 10/100/1000Mb PHYs
- RGMII/MII interface for external CPU
- Support IEEE802.3az
- Support 10/100Mb full/half duplex
- Support 1000Mb full duplex
- 100Mb TP and Fiber dual mode, selected by
Signal Detection (SD) level
Store & Forward, Share Memory
Non-blocking Architecture
- Built-in 4Mb SRAM for packet buffer
- Support 16K Jumbo packet
- Max. length 1664B without supporting jumbo
packet
Wire-Speed Operation On Every Port
Head Of Line Blocking Prevention
Flow Control
- 802.3x compliant flow control in full duplex
- Collision/Carrier_ sense based backpressure
in half duplex
Internal 16K MAC Address Entities
- CRC/Direct hashing algorithm
- Aging timer programmable (55s~500hrs)
- Wire speed address learning and resolution
- CPU accessible for security and static MAC
- Learning enable/disable
IGMP/MLD Snooping
- IGMP Version 1, 2, 3 / MLD Version 1, 2
- MLD snooping. ( 4 sets IP address per MLD
list )
- Snooping by Switch ASIC or CPU
Two Trunk Group
- Two trunk groups, trunk A~B up to 4 ports
- Load balance based on (Port ID, DA, SA,
DA/SA, IP, TCP/UTP)
- Link fault recovery
Per Port 41 MIB Counters/port
- RMON/ Ethernet/ MIB II
Hardware Auto loop detection
VLAN
- 10 Port based
- 4K Tag based
- Support Tag remove/add/modify
- IVL/SVL learning mode
- Support Protocol VLAN
- Support Q-in-Q (double tag)
- 64 configurable VID for Q-in-Q tag stacking
Class Of Service (CoS)
- Support FIFS/SP/WRR/SP+WRR/WFQ/
TWRR in Output Queue Schedule Modes
- Port based priority
- 802.1Q priority tag based
- IP TOS based (IPv4/IPv6)
- TCP/UDP port number based
- Source MAC address based
- ACL based
- Privilege priority
- 8 levels per port
Priority queuing decision
- DSCP/ TAG priority remarking
- 802.1Qad PCP, DEN insert / modify
- 802.1Q PCP, CFI insert/ modify
- RX &TX Priority re-mapping
- LLQ + latency
Broadcast/multicast/DLF/ARP/ICMP Storm
Control
- 256 levels resolution for all storm control
- Storm control can be enabled for per port
- With option to drop all ARP to CPU
- Unit time can be selected for all storm control
Sniffer Function
- Ingress,egress,ingress/egress methods
- Two Sniffer destination port group
configurations
- Add/ Remove Tag option for packet routing to
mirroring ports
- ACL and special tag for sniffer application
Port Security
- MAC based
- TCP/UDP port based
- SIP based
- 802.1x :Port based & MAC based

 

 

 



IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip






 


IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip


IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip

IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip

IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip

IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip
IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip

IP1810 8-Port 10/100 + 2-Port 10/100/1000Mb Ethernet Switch IC chip



 

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