DRAM Chip DDR2 SDRAM 512Mbit W9751G6KB-25

• Customization: Available
• Conductive Type: Unipolar Integrated Circuit
• Integration: MSI
• Model NO.: W9751G6KB-25
• Technics: Thin Film IC
• MFG.: WINBOND
• D/C: 17+
• Package: WBGA-84
• Quality: Genuine New Original
• shape: SMD
• Transport Package: Box
• Origin: China
• HS Code: 8542390000
• Production Capacity: 1000000PCS

Product Description

Description

W9751G6KB-25: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin WBGA 

Package: EBGA-84

Mfr. Part#: W9751G6KB-25

Mfr.: WINBOND

Datasheet: (e-mail or chat us for PDF file)

ROHS Status: 

Quality: 100% Original

Warranty: 180 days
 

The W9751G6KB is a 512M bits DDR2 SDRAM, organized as 8.388.608 words x 4 banks x 16 bits. This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general applications. W9751G6KB is sorted into the following speed grades: -18. 181, -25, 25L. 251 and -3. The -18/181 grade parts are compliant to the DDR2-1066 (7-7-7) specification (the 181 industrial grade which is guaranteed to support -40°C £ Tcase< 95°C). The -25/25L/25I grade parts are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 251 industrial grade which is guaranteed to support -40°C £ Tcase £ 95°C). The -3 grade parts is compliant to the DDR2-667 (5-5-5) specification.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source synchronous fashion.

 

Key Features

• Power Supply: Vdd, Vddq = 1.8 V± 0.1V
• Double Data Rate architecture: two data transfers per clock cycle
• CAS Latency: 3, 4, 5, 6 and 7
• Burst Length: 4 and 8
• Bi-directional differential data strobes (DQS and DQS) are transmitted / received with data
• Edge-aligned with Read data and center-aligned with Write data
• DLL aligns DQ and DQS transitions with clock
• Differential clock inputs (CLK and CLK)
• Data masks (DM) for write data
• Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS
• Posted CAS programmable additive latency supported to make command and data bus efficiency
• Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
• Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
• Auto-precharge operation for read and write bursts
• Auto Refresh and Self Refresh modes
• Precharged Power Down and Active Power Down
• Write Data Mask
• Write Latency = Read Latency -1 (WL = RL -1)
• Interface: SSTL_18
• Packaged in WBGA 84 Ball (8X12.5 mm2), using Lead free materials with RoHS compliant

 

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Why choosing us

• Located in Shenzhen, the electronic market center of China.
• 100% guarantee components quality: Genuine Original.
• Sufficient stock on your urgent demand.
• Sophisticated colleagues help you solve problems to reduce your risk with on-demand manufacturing
• Faster shipment: In stock components can ship the same day .
• 24 Hours service 

 

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