| shape: | SMD |
|---|---|
| Conductive Type: | Unipolar Integrated Circuit |
| Integration: | ULSI |
| Technics: | Thin Film IC |
| Application: | Standard Generalized Integrated Circuit |
| Type: | Analog IC |
| Customization: |
|---|
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Audited Supplier MT41K512M16HA-125IT:A: DRAM Chip DDR3L SDRAM 8G-Bit 512Mx16 1.35V 96-Pin F-BGA
Package: FBGA
Mfr. Part#: MT41K512M16HA-125IT:A
Mfr.: MICRON
Datasheet: 
(e-mail or chat us for PDF file)
ROHS Status:
Quality: 100% Original
Warranty: 180 days
DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM opControl, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode.
| Memory Type | Volatile | |
|---|---|---|
| Memory Format | DRAM | |
| Technology | SDRAM - DDR3L | |
| Memory Size | 8Gb (512M x 16) | |
| Clock Frequency | 800MHz | |
| Write Cycle Time - Word, Page | - | |
| Access Time | 13.5ns | |
| Memory Interface | Parallel | |
| Voltage - Supply | 1.283 V ~ 1.45 V | |
| Operating Temperature | -40°C ~ 95°C (TC) | |
| Mounting Type | Surface Mount | |
| Package / Case | 96-TFBGA | |
| Supplier Device Package | 96-FBGA (14x9) |
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